1. Field of the Invention
The present invention relates to a method of fabricating a complementary semiconductor device having a region of a first conductivity type and a region of a second conductivity type.
2. Description of the Prior Art
When a CMOS-LSI which is a complementary semiconductor device is to be fabricated, after an element isolation insulating film is formed, an impurity for forming a well region and an impurity for forming a channel stopper in the well region are ion-implanted through the element isolation insulating film, and an impurity for adjusting a threshold voltage is sequentially ion-implanted. This method has been reported (for example, IEDM88, pp. 100-103 (1988)).
According to this method, when an energy for ion implantation is properly selected, since ion implantation in an N-channel region and ion implantation in a P-channel region can be performed by steps using a total of two masks, the steps in fabricating a semiconductor device are simplified.
In order to obtain a sufficient threshold voltage of a parasitic MOS transistor even though an element isolation insulating film varies in thickness and to increase a margin against punch through in an element isolation region, the profiles of an impurity for forming a well region and an impurity for forming a channel stopper must be extended in the direction of depth of a semiconductor substrate to some extent. For this reason, annealing must be performed at 950.degree. C. in an N.sub.2 atmosphere for about 60 minutes.
In order to minimize gate swing and suppress a short channel effect of especially, a P-channel transistor, the profile of an impurity for adjusting a threshold voltage must be decreased in the direction of depth of the semiconductor substrate to effectively increase only an impurity concentration of the surface region of the semiconductor substrate. For this purpose, the above annealing at 950.degree. C. in the N.sub.2 atmosphere for about 60 minutes is excessive.
Therefore, in the prior art as described above, both the demands of increasing the margin against punch through in the element isolation region and of minimizing the gate swing cannot be simultaneously satisfied, and these demands must be traded off.